/* SPDX-License-Identifier: GPL-2.0+ */

#define PHY_IP_MUX_REG_GRP_PCIE0_L0_RESET_X_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PCIE0_L0_RESET_X_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PCIE0_L0_RESET_X_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO40_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO40_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO40_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PCIE0_L0_WAKEUP_X_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PCIE0_L0_WAKEUP_X_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PCIE0_L0_WAKEUP_X_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO41_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO41_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO41_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART2_RTS_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART2_RTS_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART2_RTS_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PCIE0_L0_CLKREQ_IN_X_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PCIE0_L0_CLKREQ_IN_X_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PCIE0_L0_CLKREQ_IN_X_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO42_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO42_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO42_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART2_CTS_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART2_CTS_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART2_CTS_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PCIE1_L0_RESET_X_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PCIE1_L0_RESET_X_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PCIE1_L0_RESET_X_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO43_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO43_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO43_MASK 0xf
#define PHY_IP_MUX_REG_GRP_CAN1_TX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_CAN1_TX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_CAN1_TX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PCIE1_L0_WAKEUP_X_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PCIE1_L0_WAKEUP_X_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PCIE1_L0_WAKEUP_X_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SATA0_DEVSLP_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SATA0_DEVSLP_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SATA0_DEVSLP_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO44_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO44_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO44_MASK 0xf
#define PHY_IP_MUX_REG_GRP_CAN1_RXD_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_CAN1_RXD_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_CAN1_RXD_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PCIE1_L0_CLKREQ_IN_X_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PCIE1_L0_CLKREQ_IN_X_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PCIE1_L0_CLKREQ_IN_X_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SATA1_DEVSLP_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SATA1_DEVSLP_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SATA1_DEVSLP_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO45_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO45_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO45_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO184_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO184_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO184_MASK 0xf
#define PHY_IP_MUX_REG_GRP_VO0_CLK_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_VO0_CLK_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_VO0_CLK_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART4_TX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART4_TX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART4_TX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_IIC0_SDA_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_IIC0_SDA_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_IIC0_SDA_MASK 0xf
#define PHY_IP_MUX_REG_GRP_VO1_CLK_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_VO1_CLK_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_VO1_CLK_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO128_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO128_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO128_MASK 0xf
#define PHY_IP_MUX_REG_GRP_VO0_D7_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_VO0_D7_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_VO0_D7_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART4_RX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART4_RX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART4_RX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_IIC0_SCL_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_IIC0_SCL_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_IIC0_SCL_MASK 0xf
#define PHY_IP_MUX_REG_GRP_VO1_D7_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_VO1_D7_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_VO1_D7_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO129_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO129_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO129_MASK 0xf
#define PHY_IP_MUX_REG_GRP_I2S0_SCLK_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_I2S0_SCLK_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_I2S0_SCLK_MASK 0xf
#define PHY_IP_MUX_REG_GRP_VO0_D8_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_VO0_D8_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_VO0_D8_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART5_TX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART5_TX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART5_TX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SPI0_CS_X_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_CS_X_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_CS_X_MASK 0xf
#define PHY_IP_MUX_REG_GRP_VO1_D8_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_VO1_D8_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_VO1_D8_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO130_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO130_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO130_MASK 0xf
#define PHY_IP_MUX_REG_GRP_I2S0_WSI_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_I2S0_WSI_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_I2S0_WSI_MASK 0xf
#define PHY_IP_MUX_REG_GRP_VO0_D9_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_VO0_D9_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_VO0_D9_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART5_RX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART5_RX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART5_RX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SPI0_SDI_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_SDI_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_SDI_MASK 0xf
#define PHY_IP_MUX_REG_GRP_VO1_D9_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_VO1_D9_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_VO1_D9_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO131_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO131_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO131_MASK 0xf
#define PHY_IP_MUX_REG_GRP_I2S0_SDI0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_I2S0_SDI0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_I2S0_SDI0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_VO0_D10_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_VO0_D10_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_VO0_D10_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART6_TX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART6_TX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART6_TX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SPI0_SDO_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_SDO_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_SDO_MASK 0xf
#define PHY_IP_MUX_REG_GRP_VO1_D10_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_VO1_D10_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_VO1_D10_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO132_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO132_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO132_MASK 0xf
#define PHY_IP_MUX_REG_GRP_I2S0_SDI1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_I2S0_SDI1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_I2S0_SDI1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_VO0_D11_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_VO0_D11_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_VO0_D11_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART6_RX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART6_RX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART6_RX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SPI0_SCK_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_SCK_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_SCK_MASK 0xf
#define PHY_IP_MUX_REG_GRP_VO1_D11_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_VO1_D11_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_VO1_D11_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO133_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO133_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO133_MASK 0xf
#define PHY_IP_MUX_REG_GRP_I2S0_SDO_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_I2S0_SDO_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_I2S0_SDO_MASK 0xf
#define PHY_IP_MUX_REG_GRP_CAN1_TX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_CAN1_TX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_CAN1_TX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_VO0_D12_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_VO0_D12_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_VO0_D12_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART7_TX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART7_TX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART7_TX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART4_RTS_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART4_RTS_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART4_RTS_MASK 0xf
#define PHY_IP_MUX_REG_GRP_VO1_D12_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_VO1_D12_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_VO1_D12_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO134_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO134_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO134_MASK 0xf
#define PHY_IP_MUX_REG_GRP_I2S0_MCLK_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_I2S0_MCLK_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_I2S0_MCLK_MASK 0xf
#define PHY_IP_MUX_REG_GRP_CAN1_RXD_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_CAN1_RXD_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_CAN1_RXD_MASK 0xf
#define PHY_IP_MUX_REG_GRP_VO0_D13_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_VO0_D13_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_VO0_D13_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART7_RX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART7_RX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART7_RX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART4_CTS_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART4_CTS_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART4_CTS_MASK 0xf
#define PHY_IP_MUX_REG_GRP_VO1_D13_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_VO1_D13_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_VO1_D13_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII0_TXD0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_TXD0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_TXD0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM4_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM4_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM4_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO8_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO8_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO8_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII0_TXD1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_TXD1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_TXD1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM5_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM5_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM5_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO9_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO9_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO9_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII0_TXD2_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_TXD2_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_TXD2_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM6_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM6_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM6_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO10_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO10_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO10_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII0_TXD3_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_TXD3_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_TXD3_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM7_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM7_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM7_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO11_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO11_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO11_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII0_TXCTRL_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_TXCTRL_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_TXCTRL_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM8_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM8_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM8_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO12_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO12_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO12_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII0_RXD0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_RXD0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_RXD0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM9_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM9_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM9_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO13_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO13_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO13_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII0_RXD1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_RXD1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_RXD1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM10_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM10_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM10_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO14_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO14_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO14_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII0_RXD2_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_RXD2_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_RXD2_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM11_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM11_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM11_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO15_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO15_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO15_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII0_RXD3_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_RXD3_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_RXD3_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM12_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM12_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM12_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO16_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO16_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO16_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII0_RXCTRL_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_RXCTRL_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_RXCTRL_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM13_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM13_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM13_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO17_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO17_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO17_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII0_TXC_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_TXC_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_TXC_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM14_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM14_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM14_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO18_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO18_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO18_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII0_RXC_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_RXC_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_RXC_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM15_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM15_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM15_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO19_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO19_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO19_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII0_REFCLKO_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_REFCLKO_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_REFCLKO_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM16_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM16_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM16_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO20_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO20_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO20_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII0_IRQ_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_IRQ_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_IRQ_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM17_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM17_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM17_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO21_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO21_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO21_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII0_MDC_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_MDC_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_MDC_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM18_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM18_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM18_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO22_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO22_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO22_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII0_MDIO_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_MDIO_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII0_MDIO_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM19_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM19_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM19_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO23_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO23_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO23_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII1_TXD0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_TXD0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_TXD0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM4_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM4_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM4_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO24_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO24_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO24_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII1_TXD1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_TXD1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_TXD1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM5_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM5_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM5_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO25_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO25_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO25_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII1_TXD2_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_TXD2_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_TXD2_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM6_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM6_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM6_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO26_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO26_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO26_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII1_TXD3_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_TXD3_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_TXD3_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM7_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM7_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM7_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO27_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO27_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO27_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII1_TXCTRL_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_TXCTRL_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_TXCTRL_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM8_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM8_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM8_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO28_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO28_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO28_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII1_RXD0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_RXD0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_RXD0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM9_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM9_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM9_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO29_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO29_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO29_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII1_RXD1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_RXD1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_RXD1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM10_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM10_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM10_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO30_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO30_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO30_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII1_RXD2_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_RXD2_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_RXD2_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM11_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM11_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM11_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO31_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO31_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO31_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII1_RXD3_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_RXD3_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_RXD3_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM12_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM12_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM12_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO32_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO32_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO32_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII1_RXCTRL_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_RXCTRL_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_RXCTRL_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM13_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM13_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM13_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO33_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO33_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO33_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII1_TXC_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_TXC_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_TXC_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM14_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM14_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM14_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO34_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO34_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO34_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII1_RXC_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_RXC_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_RXC_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM15_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM15_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM15_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO35_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO35_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO35_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII1_REFCLKO_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_REFCLKO_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_REFCLKO_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM16_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM16_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM16_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO36_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO36_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO36_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII1_IRQ_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_IRQ_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_IRQ_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM17_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM17_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM17_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO37_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO37_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO37_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII1_MDC_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_MDC_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_MDC_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM18_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM18_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM18_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO38_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO38_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO38_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RGMII1_MDIO_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_MDIO_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RGMII1_MDIO_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM19_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM19_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM19_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO39_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO39_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO39_MASK 0xf
#define PHY_IP_MUX_REG_GRP_C906_JTAG0_TDI_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_C906_JTAG0_TDI_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_C906_JTAG0_TDI_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART2_RTS_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART2_RTS_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART2_RTS_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SD2_1_D2_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SD2_1_D2_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SD2_1_D2_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO89_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO89_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO89_MASK 0xf
#define PHY_IP_MUX_REG_GRP_KEY_COL2_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_KEY_COL2_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_KEY_COL2_MASK 0xf
#define PHY_IP_MUX_REG_GRP_C906_JTAG0_TMS_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_C906_JTAG0_TMS_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_C906_JTAG0_TMS_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART2_CTS_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART2_CTS_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART2_CTS_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SD2_1_D3_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SD2_1_D3_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SD2_1_D3_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO90_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO90_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO90_MASK 0xf
#define PHY_IP_MUX_REG_GRP_KEY_COL3_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_KEY_COL3_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_KEY_COL3_MASK 0xf
#define PHY_IP_MUX_REG_GRP_C906_JTAG0_TCK_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_C906_JTAG0_TCK_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_C906_JTAG0_TCK_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SD2_1_D1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SD2_1_D1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SD2_1_D1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO88_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO88_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO88_MASK 0xf
#define PHY_IP_MUX_REG_GRP_KEY_COL1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_KEY_COL1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_KEY_COL1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_RSTN_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_RSTN_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_RSTN_MASK 0xf
#define PHY_IP_MUX_REG_GRP_C906_JTAG0_TDO_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_C906_JTAG0_TDO_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_C906_JTAG0_TDO_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SD2_1_D0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SD2_1_D0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SD2_1_D0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO87_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO87_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO87_MASK 0xf
#define PHY_IP_MUX_REG_GRP_KEY_COL0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_KEY_COL0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_KEY_COL0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART4_TX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART4_TX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART4_TX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SD2_1_CLK_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SD2_1_CLK_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SD2_1_CLK_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO91_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO91_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO91_MASK 0xf
#define PHY_IP_MUX_REG_GRP_KEY_ROW0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_KEY_ROW0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_KEY_ROW0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART4_RX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART4_RX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART4_RX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SD2_1_CMD_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SD2_1_CMD_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SD2_1_CMD_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO92_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO92_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO92_MASK 0xf
#define PHY_IP_MUX_REG_GRP_KEY_ROW1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_KEY_ROW1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_KEY_ROW1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART4_RTS_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART4_RTS_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART4_RTS_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO93_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO93_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO93_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART3_RTS_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART3_RTS_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART3_RTS_MASK 0xf
#define PHY_IP_MUX_REG_GRP_KEY_ROW2_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_KEY_ROW2_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_KEY_ROW2_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART4_CTS_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART4_CTS_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART4_CTS_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO94_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO94_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO94_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART3_CTS_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART3_CTS_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART3_CTS_MASK 0xf
#define PHY_IP_MUX_REG_GRP_KEY_ROW3_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_KEY_ROW3_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_KEY_ROW3_MASK 0xf
#define PHY_IP_MUX_REG_GRP_DBG_I2C_SCL_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_DBG_I2C_SCL_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_DBG_I2C_SCL_MASK 0xf
#define PHY_IP_MUX_REG_GRP_IIC0_SDA_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_IIC0_SDA_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_IIC0_SDA_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO95_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO95_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO95_MASK 0xf
#define PHY_IP_MUX_REG_GRP_DBG_I2C_SDA_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_DBG_I2C_SDA_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_DBG_I2C_SDA_MASK 0xf
#define PHY_IP_MUX_REG_GRP_IIC0_SCL_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_IIC0_SCL_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_IIC0_SCL_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO96_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO96_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO96_MASK 0xf
#define PHY_IP_MUX_REG_GRP_ADC1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_ADC1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_ADC1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO120_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO120_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO120_MASK 0xf
#define PHY_IP_MUX_REG_GRP_ADC2_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_ADC2_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_ADC2_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO121_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO121_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO121_MASK 0xf
#define PHY_IP_MUX_REG_GRP_ADC3_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_ADC3_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_ADC3_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO122_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO122_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO122_MASK 0xf
#define PHY_IP_MUX_REG_GRP_TEMPSEN_BJT_ANA_TOUT_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_TEMPSEN_BJT_ANA_TOUT_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_TEMPSEN_BJT_ANA_TOUT_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO123_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO123_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO123_MASK 0xf
#define PHY_IP_MUX_REG_GRP_C906_JTAG0_TRST_X_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_C906_JTAG0_TRST_X_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_C906_JTAG0_TRST_X_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO97_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO97_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO97_MASK 0xf
#define PHY_IP_MUX_REG_GRP_C906_JTAG0_SRST_X_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_C906_JTAG0_SRST_X_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_C906_JTAG0_SRST_X_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO98_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO98_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO98_MASK 0xf
#define PHY_IP_MUX_REG_GRP_TC906_JTAG0_TDO_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_TC906_JTAG0_TDO_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_TC906_JTAG0_TDO_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO99_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO99_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO99_MASK 0xf
#define PHY_IP_MUX_REG_GRP_TC906_JTAG0_TDI_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_TC906_JTAG0_TDI_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_TC906_JTAG0_TDI_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO100_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO100_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO100_MASK 0xf
#define PHY_IP_MUX_REG_GRP_KEY_ROW0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_KEY_ROW0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_KEY_ROW0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_TC906_JTAG0_TCK_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_TC906_JTAG0_TCK_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_TC906_JTAG0_TCK_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO101_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO101_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO101_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART5_TX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART5_TX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART5_TX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_KEY_ROW1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_KEY_ROW1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_KEY_ROW1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_TC906_JTAG0_TMS_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_TC906_JTAG0_TMS_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_TC906_JTAG0_TMS_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO102_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO102_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO102_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART5_RX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART5_RX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART5_RX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_KEY_ROW2_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_KEY_ROW2_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_KEY_ROW2_MASK 0xf
#define PHY_IP_MUX_REG_GRP_TC906_JTAG0_TRST_X_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_TC906_JTAG0_TRST_X_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_TC906_JTAG0_TRST_X_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO103_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO103_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO103_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART6_TX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART6_TX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART6_TX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_KEY_ROW3_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_KEY_ROW3_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_KEY_ROW3_MASK 0xf
#define PHY_IP_MUX_REG_GRP_TC906_JTAG0_SRST_X_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_TC906_JTAG0_SRST_X_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_TC906_JTAG0_SRST_X_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO104_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO104_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO104_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART6_RX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART6_RX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART6_RX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SD1_CD_X_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SD1_CD_X_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SD1_CD_X_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM14_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM14_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM14_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO61_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO61_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO61_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SD1_PWR_EN_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SD1_PWR_EN_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SD1_PWR_EN_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO68_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO68_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO68_MASK 0xf
#define PHY_IP_MUX_REG_GRP_A53_JTAG0_TDO_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_A53_JTAG0_TDO_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_A53_JTAG0_TDO_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO111_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO111_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO111_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM8_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM8_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM8_MASK 0xf
#define PHY_IP_MUX_REG_GRP_A53_JTAG0_TCK_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_A53_JTAG0_TCK_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_A53_JTAG0_TCK_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO112_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO112_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO112_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM9_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM9_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM9_MASK 0xf
#define PHY_IP_MUX_REG_GRP_A53_JTAG0_TDI_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_A53_JTAG0_TDI_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_A53_JTAG0_TDI_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO113_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO113_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO113_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART2_RTS_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART2_RTS_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART2_RTS_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM10_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM10_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM10_MASK 0xf
#define PHY_IP_MUX_REG_GRP_A53_JTAG0_TMS_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_A53_JTAG0_TMS_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_A53_JTAG0_TMS_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO114_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO114_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO114_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART2_CTS_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART2_CTS_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART2_CTS_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM11_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM11_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM11_MASK 0xf
#define PHY_IP_MUX_REG_GRP_A53_JTAG0_TRST_X_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_A53_JTAG0_TRST_X_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_A53_JTAG0_TRST_X_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO115_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO115_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO115_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM12_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM12_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM12_MASK 0xf
#define PHY_IP_MUX_REG_GRP_A53_JTAG0_SRST_X_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_A53_JTAG0_SRST_X_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_A53_JTAG0_SRST_X_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO116_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO116_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO116_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM13_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM13_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM13_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO117_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO117_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO117_MASK 0xf
#define PHY_IP_MUX_REG_GRP_WG0_D0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_WG0_D0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_WG0_D0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_CAN1_TX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_CAN1_TX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_CAN1_TX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM14_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM14_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM14_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO118_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO118_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO118_MASK 0xf
#define PHY_IP_MUX_REG_GRP_WG0_D1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_WG0_D1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_WG0_D1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_CAN1_RXD_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_CAN1_RXD_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_CAN1_RXD_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM15_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM15_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM15_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART0_TX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART0_TX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART0_TX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO81_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO81_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO81_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART0_RX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART0_RX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART0_RX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO82_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO82_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO82_MASK 0xf
#define PHY_IP_MUX_REG_GRP_DBG_I2C_SCL_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_DBG_I2C_SCL_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_DBG_I2C_SCL_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO83_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO83_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO83_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO85_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO85_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO85_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART5_TX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART5_TX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART5_TX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_DBG_I2C_SDA_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_DBG_I2C_SDA_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_DBG_I2C_SDA_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO84_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO84_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO84_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO86_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO86_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO86_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART5_RX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART5_RX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART5_RX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_EMMC_RST_X_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_EMMC_RST_X_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_EMMC_RST_X_MASK 0xf
#define PHY_IP_MUX_REG_GRP_EMMC_CLK_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_EMMC_CLK_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_EMMC_CLK_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SPINOR_SCK_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SPINOR_SCK_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SPINOR_SCK_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SPINAND_SCK_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SPINAND_SCK_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SPINAND_SCK_MASK 0xf
#define PHY_IP_MUX_REG_GRP_EMMC_CMD_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_EMMC_CMD_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_EMMC_CMD_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SPINOR_SDI_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SPINOR_SDI_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SPINOR_SDI_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SPINAND_SDI_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SPINAND_SDI_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SPINAND_SDI_MASK 0xf
#define PHY_IP_MUX_REG_GRP_EMMC_D0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_EMMC_D0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_EMMC_D0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SPINOR_SDO_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SPINOR_SDO_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SPINOR_SDO_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SPINAND_SDO_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SPINAND_SDO_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SPINAND_SDO_MASK 0xf
#define PHY_IP_MUX_REG_GRP_EMMC_D1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_EMMC_D1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_EMMC_D1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SPINOR_CS_X_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SPINOR_CS_X_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SPINOR_CS_X_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SPINAND_CS_X_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SPINAND_CS_X_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SPINAND_CS_X_MASK 0xf
#define PHY_IP_MUX_REG_GRP_EMMC_D2_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_EMMC_D2_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_EMMC_D2_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SPINOR_HOLD_X_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SPINOR_HOLD_X_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SPINOR_HOLD_X_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SPINAND_HOLD_X_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SPINAND_HOLD_X_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SPINAND_HOLD_X_MASK 0xf
#define PHY_IP_MUX_REG_GRP_EMMC_D3_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_EMMC_D3_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_EMMC_D3_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SPINOR_WP_X_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SPINOR_WP_X_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SPINOR_WP_X_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SPINAND_WP_X_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SPINAND_WP_X_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SPINAND_WP_X_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SD1_CLK_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SD1_CLK_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SD1_CLK_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM15_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM15_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM15_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO62_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO62_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO62_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SD1_CMD_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SD1_CMD_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SD1_CMD_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM16_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM16_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM16_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO63_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO63_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO63_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SD1_D0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SD1_D0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SD1_D0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM17_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM17_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM17_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO64_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO64_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO64_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SD1_D1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SD1_D1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SD1_D1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM18_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM18_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM18_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO65_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO65_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO65_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART7_TX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART7_TX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART7_TX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SD1_D2_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SD1_D2_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SD1_D2_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM19_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM19_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM19_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO66_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO66_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO66_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART7_RX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART7_RX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART7_RX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SD1_D3_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SD1_D3_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SD1_D3_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO67_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO67_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO67_MASK 0xf
#define PHY_IP_MUX_REG_GRP_CAN0_TX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_CAN0_TX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_CAN0_TX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_WG0_D0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_WG0_D0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_WG0_D0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO105_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO105_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO105_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART2_RTS_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART2_RTS_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART2_RTS_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM2_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM2_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM2_MASK 0xf
#define PHY_IP_MUX_REG_GRP_CAN0_RXD_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_CAN0_RXD_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_CAN0_RXD_MASK 0xf
#define PHY_IP_MUX_REG_GRP_WG0_D1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_WG0_D1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_WG0_D1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO106_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO106_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO106_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART2_CTS_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART2_CTS_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART2_CTS_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM3_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM3_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM3_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO46_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO46_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO46_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO47_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO47_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO47_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO48_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO48_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO48_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO49_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO49_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO49_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO50_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO50_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO50_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO51_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO51_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO51_MASK 0xf
#define PHY_IP_MUX_REG_GRP_CAM_XLR0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_CAM_XLR0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_CAM_XLR0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO69_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO69_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO69_MASK 0xf
#define PHY_IP_MUX_REG_GRP_CAM_XLR1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_CAM_XLR1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_CAM_XLR1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO70_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO70_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO70_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_HDMI_DDC_SDA_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_HDMI_DDC_SDA_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_HDMI_DDC_SDA_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO71_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO71_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO71_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_HDMI_DDC_SCL_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_HDMI_DDC_SCL_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_HDMI_DDC_SCL_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO72_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO72_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO72_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PKG_TYPE_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PKG_TYPE_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PKG_TYPE_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO6_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO6_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO6_MASK 0xf
#define PHY_IP_MUX_REG_GRP_AUX0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_AUX0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_AUX0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO7_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO7_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO7_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_KEY_COL0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_KEY_COL0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_KEY_COL0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SD2_0_CLK_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SD2_0_CLK_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SD2_0_CLK_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO75_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO75_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO75_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART5_TX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART5_TX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART5_TX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_KEY_COL1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_KEY_COL1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_KEY_COL1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SD2_0_CMD_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SD2_0_CMD_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SD2_0_CMD_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO76_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO76_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO76_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART5_RX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART5_RX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART5_RX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM2_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM2_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM2_MASK 0xf
#define PHY_IP_MUX_REG_GRP_KEY_COL2_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_KEY_COL2_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_KEY_COL2_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SD2_0_D0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SD2_0_D0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SD2_0_D0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO77_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO77_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO77_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART6_TX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART6_TX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART6_TX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM3_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM3_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM3_MASK 0xf
#define PHY_IP_MUX_REG_GRP_KEY_COL3_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_KEY_COL3_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_KEY_COL3_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SD2_0_D1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SD2_0_D1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SD2_0_D1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO78_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO78_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO78_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART6_RX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART6_RX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART6_RX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_TEST_EN_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_TEST_EN_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_TEST_EN_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SD0_CD_X_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SD0_CD_X_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SD0_CD_X_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM6_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM6_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM6_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO53_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO53_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO53_MASK 0xf
#define PHY_IP_MUX_REG_GRP_IIC0_SDA_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_IIC0_SDA_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_IIC0_SDA_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SD0_PWR_EN_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SD0_PWR_EN_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SD0_PWR_EN_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM13_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM13_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM13_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO60_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO60_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO60_MASK 0xf
#define PHY_IP_MUX_REG_GRP_IIC0_SCL_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_IIC0_SCL_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_IIC0_SCL_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM4_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM4_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM4_MASK 0xf
#define PHY_IP_MUX_REG_GRP_CAN1_TX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_CAN1_TX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_CAN1_TX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SD2_0_D2_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SD2_0_D2_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SD2_0_D2_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO79_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO79_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO79_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART4_TX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART4_TX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART4_TX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM5_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM5_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM5_MASK 0xf
#define PHY_IP_MUX_REG_GRP_CAN1_RXD_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_CAN1_RXD_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_CAN1_RXD_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SD2_0_D3_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SD2_0_D3_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SD2_0_D3_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO80_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO80_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO80_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART4_RX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART4_RX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART4_RX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SPI0_CS_X_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_CS_X_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_CS_X_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO107_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO107_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO107_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART6_TX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART6_TX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART6_TX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM4_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM4_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM4_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SPI0_SDI_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_SDI_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_SDI_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO108_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO108_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO108_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART6_RX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART6_RX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART6_RX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM5_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM5_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM5_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SPI0_SDO_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_SDO_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_SDO_MASK 0xf
#define PHY_IP_MUX_REG_GRP_WG0_D0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_WG0_D0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_WG0_D0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO109_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO109_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO109_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART7_TX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART7_TX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART7_TX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM6_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM6_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM6_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SPI0_SCK_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_SCK_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_SCK_MASK 0xf
#define PHY_IP_MUX_REG_GRP_WG0_D1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_WG0_D1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_WG0_D1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO110_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO110_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO110_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART7_RX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART7_RX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART7_RX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM7_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM7_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM7_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SD0_CLK_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SD0_CLK_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SD0_CLK_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM7_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM7_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM7_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO54_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO54_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO54_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SD0_CMD_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SD0_CMD_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SD0_CMD_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM8_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM8_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM8_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO55_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO55_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO55_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SD0_D0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SD0_D0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SD0_D0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM9_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM9_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM9_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO56_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO56_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO56_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SPI0_SCK_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_SCK_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_SCK_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SD0_D1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SD0_D1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SD0_D1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM10_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM10_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM10_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO57_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO57_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO57_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SPI0_CS_X_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_CS_X_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_CS_X_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SD0_D2_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SD0_D2_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SD0_D2_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM11_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM11_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM11_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO58_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO58_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO58_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SPI0_SDI_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_SDI_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_SDI_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SD0_D3_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SD0_D3_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SD0_D3_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM12_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM12_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM12_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO59_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO59_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO59_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SPI0_SDO_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_SDO_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_SDO_MASK 0xf
#define PHY_IP_MUX_REG_GRP_CLK_25M_OUT_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_CLK_25M_OUT_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_CLK_25M_OUT_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO119_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO119_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO119_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PLL_LOCKO_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PLL_LOCKO_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PLL_LOCKO_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_ON_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_ON_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_ON_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_GPIO7_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO7_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO7_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_BUTTON1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_BUTTON1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_BUTTON1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_GPIO8_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO8_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO8_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_WAKEUP0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_WAKEUP0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_WAKEUP0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_IRRX0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_IRRX0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_IRRX0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_GPIO9_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO9_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO9_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART0_TX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART0_TX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART0_TX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_IIC_SDA_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_IIC_SDA_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_IIC_SDA_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_WAKEUP1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_WAKEUP1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_WAKEUP1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_IRRX1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_IRRX1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_IRRX1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_GPIO10_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO10_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO10_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART0_RX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART0_RX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART0_RX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_IIC_SCL_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_IIC_SCL_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_IIC_SCL_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_SEQ1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_SEQ1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_SEQ1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_GPIO11_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO11_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO11_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_SEQ2_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_SEQ2_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_SEQ2_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_GPIO12_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO12_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO12_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_SEQ3_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_SEQ3_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_SEQ3_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_GPIO13_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO13_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO13_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_IIC_SDA_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_IIC_SDA_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_IIC_SDA_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_GPIO14_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO14_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO14_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART4_TX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART4_TX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART4_TX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM16_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM16_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM16_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_IIC_SCL_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_IIC_SCL_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_IIC_SCL_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_GPIO15_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO15_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO15_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART4_RX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART4_RX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART4_RX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM17_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM17_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM17_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_UART_TX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_UART_TX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_UART_TX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_GPIO16_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO16_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO16_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM18_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM18_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM18_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_UART_RX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_UART_RX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_UART_RX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_GPIO17_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO17_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO17_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM19_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM19_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM19_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_SAR0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_SAR0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_SAR0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_GPIO0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART3_RTS_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART3_RTS_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART3_RTS_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_SPINOR_HOLD_X_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_SPINOR_HOLD_X_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_SPINOR_HOLD_X_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_GPIO1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_SAR1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_SAR1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_SAR1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART7_TX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART7_TX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART7_TX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART3_CTS_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART3_CTS_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART3_CTS_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_SPINOR_WP_X_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_SPINOR_WP_X_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_SPINOR_WP_X_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_GPIO2_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO2_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO2_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART7_RX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART7_RX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART7_RX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_SPINOR_CS_X_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_SPINOR_CS_X_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_SPINOR_CS_X_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_GPIO3_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO3_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO3_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_SPINOR_SDI_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_SPINOR_SDI_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_SPINOR_SDI_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_GPIO4_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO4_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO4_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_SPINOR_SDO_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_SPINOR_SDO_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_SPINOR_SDO_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_GPIO5_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO5_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO5_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_SPINOR_SCK_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_SPINOR_SCK_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_SPINOR_SCK_MASK 0xf
#define PHY_IP_MUX_REG_GRP_CAM_MCLK6_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_CAM_MCLK6_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_CAM_MCLK6_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_GPIO6_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO6_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_GPIO6_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_RSTN_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_RSTN_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_RSTN_MASK 0xf
#define PHY_IP_MUX_REG_GRP_CLK_25M_SEL_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_CLK_25M_SEL_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_CLK_25M_SEL_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_XTAL_XIN_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_XTAL_XIN_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_XTAL_XIN_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWR_XTAL_XOUT_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWR_XTAL_XOUT_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWR_XTAL_XOUT_MASK 0xf
#define PHY_IP_MUX_REG_GRP_I2S0_SCLK_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_I2S0_SCLK_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_I2S0_SCLK_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART5_TX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART5_TX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART5_TX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SPI0_CS_X_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_CS_X_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_CS_X_MASK 0xf
#define PHY_IP_MUX_REG_GRP_KEY_ROW0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_KEY_ROW0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_KEY_ROW0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_I2S0_WSI_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_I2S0_WSI_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_I2S0_WSI_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART5_RX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART5_RX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART5_RX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SPI0_SDI_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_SDI_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_SDI_MASK 0xf
#define PHY_IP_MUX_REG_GRP_KEY_ROW1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_KEY_ROW1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_KEY_ROW1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_I2S0_SDI0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_I2S0_SDI0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_I2S0_SDI0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM2_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM2_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM2_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO2_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO2_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO2_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART6_TX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART6_TX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART6_TX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SPI0_SDO_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_SDO_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_SDO_MASK 0xf
#define PHY_IP_MUX_REG_GRP_KEY_ROW2_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_KEY_ROW2_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_KEY_ROW2_MASK 0xf
#define PHY_IP_MUX_REG_GRP_I2S0_SDI1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_I2S0_SDI1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_I2S0_SDI1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM3_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM3_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM3_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO3_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO3_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO3_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART6_RX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART6_RX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART6_RX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_SPI0_SCK_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_SCK_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_SPI0_SCK_MASK 0xf
#define PHY_IP_MUX_REG_GRP_KEY_ROW3_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_KEY_ROW3_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_KEY_ROW3_MASK 0xf
#define PHY_IP_MUX_REG_GRP_I2S0_SDO_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_I2S0_SDO_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_I2S0_SDO_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM4_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM4_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM4_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO4_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO4_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO4_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART7_TX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART7_TX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART7_TX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_I2S0_MCLK_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_I2S0_MCLK_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_I2S0_MCLK_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PWM5_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PWM5_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PWM5_MASK 0xf
#define PHY_IP_MUX_REG_GRP_GPIO5_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_GPIO5_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_GPIO5_MASK 0xf
#define PHY_IP_MUX_REG_GRP_UART7_RX_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_UART7_RX_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_UART7_RX_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX0P_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX0P_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX0P_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX0N_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX0N_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX0N_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX1P_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX1P_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX1P_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX1N_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX1N_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX1N_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX2P_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX2P_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX2P_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX2N_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX2N_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX2N_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX3P_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX3P_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX3P_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX3N_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX3N_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX3N_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX4P_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX4P_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX4P_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX4N_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX4N_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX4N_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX5P_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX5P_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX5P_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX5N_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX5N_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX5N_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX6P_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX6P_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX6P_MASK 0xf
#define PHY_IP_MUX_REG_GRP_VI0_CLK1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_VI0_CLK1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_VI0_CLK1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX6N_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX6N_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX6N_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX7P_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX7P_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX7P_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX7N_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX7N_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX7N_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX8P_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX8P_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX8P_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX8N_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX8N_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX8N_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX9P_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX9P_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX9P_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX9N_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX9N_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX9N_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX10P_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX10P_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX10P_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX10N_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX10N_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX10N_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX11P_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX11P_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX11P_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX11N_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX11N_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX11N_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX12P_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX12P_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX12P_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX12N_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX12N_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX12N_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX13P_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX13P_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX13P_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX13N_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX13N_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX13N_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX14P_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX14P_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX14P_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX14N_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX14N_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX14N_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX15P_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX15P_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX15P_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX15N_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX15N_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX15N_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX16P_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX16P_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX16P_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX16N_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX16N_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX16N_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX17P_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX17P_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX17P_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI_RX17N_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX17N_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI_RX17N_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI0_TX0P_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI0_TX0P_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI0_TX0P_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI0_TX0N_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI0_TX0N_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI0_TX0N_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI0_TX1P_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI0_TX1P_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI0_TX1P_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI0_TX1N_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI0_TX1N_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI0_TX1N_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI0_TX2P_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI0_TX2P_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI0_TX2P_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI0_TX2N_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI0_TX2N_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI0_TX2N_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI0_TX3P_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI0_TX3P_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI0_TX3P_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI0_TX3N_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI0_TX3N_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI0_TX3N_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI0_TX4P_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI0_TX4P_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI0_TX4P_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI0_TX4N_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI0_TX4N_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI0_TX4N_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI1_TX0P_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI1_TX0P_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI1_TX0P_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI1_TX0N_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI1_TX0N_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI1_TX0N_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI1_TX1P_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI1_TX1P_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI1_TX1P_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI1_TX1N_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI1_TX1N_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI1_TX1N_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI1_TX2P_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI1_TX2P_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI1_TX2P_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI1_TX2N_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI1_TX2N_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI1_TX2N_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI1_TX3P_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI1_TX3P_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI1_TX3P_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI1_TX3N_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI1_TX3N_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI1_TX3N_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI1_TX4P_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI1_TX4P_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI1_TX4P_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_MIPI1_TX4N_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI1_TX4N_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_MIPI1_TX4N_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_AINL0_MIC_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_AINL0_MIC_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_AINL0_MIC_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_AINR0_MIC_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_AINR0_MIC_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_AINR0_MIC_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_AINL1_MIC_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_AINL1_MIC_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_AINL1_MIC_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_AINR1_MIC_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_AINR1_MIC_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_AINR1_MIC_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_AOUTL0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_AOUTL0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_AOUTL0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_AOUTR0_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_AOUTR0_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_AOUTR0_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_AOUTL1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_AOUTL1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_AOUTL1_MASK 0xf
#define PHY_IP_MUX_REG_GRP_PAD_AOUTR1_SEL PINMUX_INVALID_SEL
#define PHY_IP_MUX_REG_GRP_SEL_PAD_AOUTR1_OFFSET 0
#define PHY_IP_MUX_REG_GRP_SEL_PAD_AOUTR1_MASK 0xf
